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CPU cache
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#	Item
761	SWICH: A PROTOTYPE FOR EFFICIENT CACHE-LEVEL CHECKPOINTING AND ROLLBACK EXISTING CACHE-LEVEL CHECKPOINTING SCHEMES DO NOT CONTINUOUSLY SUPPORT A LARGE ROLLBACK WINDOW. IMMEDIATELY AFTER A CHECKPOINT, THE NUMBER OF INSTRU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-05-03 11:36:50 Computer memory Computer engineering Cache Application checkpointing CPU cache Microarchitecture SPARC64 Memory hierarchy Runahead Computer hardware Computer architecture Central processing unit
762	DeAliaser: Alias Speculation Using Atomic Region Support Wonsun Ahn Yuelu Duan Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:44:16 Software engineering Programming language implementation Central processing unit Computer memory Compiler construction Alias analysis CPU cache Loop unwinding Linearizability Computing Computer architecture Compiler optimizations
763	do i:[removed][removed] Two Hardware-Based Approaches for Deterministic Multiprocessor Replay By Derek R. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, and Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-26 23:39:42 Central processing unit Parallel computing Chunk Process CPU cache Computer architecture Computing Computer hardware Computer memory
764	Encyclopedia of Parallel Computing “00166” — [removed] — 14:04 — Page 1 — #2 C  Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-05-19 11:47:48 Parallel computing Non-Uniform Memory Access Cache-only memory architecture CPU cache Memory architecture Uniform memory access Kendall Square Research Cache Random-access memory Computing Computer memory Concurrent computing
765	L1 Data Cache Decomposition for Energy Efficiency Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 11:58:14 Cache CPU cache Computer architecture Computing R10000 Computer hardware Central processing unit Computer memory
766	PostgreSQL Performance Tuning Add to Reading List Source URL: momjian.us Language: English - Date: 2015-04-15 18:13:51 Cross-platform software PostgreSQL Computer memory GiST Cache Sync Disk buffer CPU cache Performance tuning Software Computing Computer hardware
767	Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy Ehsan Totoni, Josep Torrellas, Laxmikant V. Kale Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA E Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-08-13 13:31:19 Computer memory Computer hardware CPU cache Central processing unit Instruction set architectures Cache algorithms Memory hierarchy Blue Gene Xeon Computer architecture Computing Cache
768	Characterizing the Impact of End-System Affinities On the End-to-End Performance of High-Speed Flows Nathan Hanford1 , Vishal Ahuja1 , Mehmet Balman2 , Matthew K. Farrens1 , Dipak Ghosal1 , Eric Pouyoul2 and Brian Tierne Add to Reading List Source URL: www.es.net Language: English - Date: 2014-12-11 12:32:11 Computer memory Scheduling algorithms Microprocessors Computer architecture Multi-core processor Parallel computing AMD 10h Jumbo frame CPU cache Computing Computer hardware Concurrent computing
769	Prof. Dr.-Ing. Dr. h. c. mult. P. J. Kühn Prof. Dr.-Ing. Dr. h. c. mult. P. J. Kühn International Symposium on Memory Management June 10–11, 2006 Ottawa, Canada Add to Reading List Source URL: www.cs.technion.ac.il Language: English - Date: 2010-02-20 10:44:16 Computing Pointer Garbage collection Classic RISC pipeline Microarchitecture Processor register CPU cache Instruction set Memory barrier Computer hardware Computer architecture Central processing unit
770	Alpha[removed]EV6 Microprocessor Hardware Reference Manual Order Number: DS–0027C–TE This manual is directly derived from the internal[removed]EV6 Specifications, Revision 4.5. You can access this hardware reference manu Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:04:20 Computer engineering DEC Alpha PALcode Alpha 21264 CPU cache Branch predictor Processor register Instruction set Computer architecture Computer hardware Central processing unit

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